Architect, AI Solutions – Digital IP Methodology & Solutions

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an accomplished engineer with a passion for physical design and a drive to solve complex challenges in advanced semiconductor technology. With 20+ years of hands-on experience in the complete RTL-to-GDS flow, you thrive on collaborating with customers and internal teams to deliver innovative, high-value solutions. Your expertise spans advanced nodes, synthesis, design planning, and place & route, complemented by a strong command of timing closure, power reduction methodologies, DRC rules, and formal verification. You are adept at leveraging industry-leading EDA tools such as Fusion Compiler, PrimeTime, PrimeClosure, Formality, DSO.ai, FusionAI, ICV, StarRC, and RTLA, and you are well versed with AI/ML applications, building and deploying AI Agents.

You excel in dynamic, high-performance teams, proactively sharing knowledge and mentoring peers. Your communication skills enable you to translate technical complexities into actionable insights for both customers and colleagues. You are innovative, adaptable, and eager to stay ahead in a fast-evolving domain. Your passion for continuous learning and improvement drives you to explore new methodologies, ensuring customer success and the advancement of Synopsys’ cutting-edge tools.

Above all, you are motivated by the impact of your work on the semiconductor industry and the broader technology landscape. You are ready to be a technical leader and trusted advisor, shaping the future of physical design and pushing the boundaries of what’s possible.

What You’ll Be Doing:

• Engaging directly with Synopsys customers to understand their design goals, challenges, and requirements, building tailored solutions that maximize their productivity and success.
• Demonstrating the unique advantages and capabilities of Synopsys’ industry-leading physical design tools, including Fusion Compiler, PrimeTime, and DSO.ai, through hands-on support and customer enablement activities.
• Collaborating closely with Synopsys R&D and Product Engineering teams to influence tool development, provide feedback from the field, and drive enhancements that address real-world design challenges.
• Delivering technical presentations, workshops, and training sessions to empower customers and internal teams with best practices in synthesis, place & route, timing closure, and power optimization.
• Diagnosing and resolving complex design issues, providing expert guidance on advanced node challenges, DRC closure, ECO flows, and formal verification methodologies.
• Contributing to the productivity and growth of the Application Engineering team by sharing expertise, developing technical collateral, and mentoring junior engineers.

The Impact You Will Have:

• Accelerate customer success by ensuring smooth adoption and optimal use of Synopsys’ physical design solutions across advanced technology nodes.
• Drive innovation in EDA tool development by channeling customer feedback and real-world requirements directly to Synopsys R&D teams.
• Enhance the industry’s most advanced chip design flows, enabling customers to achieve faster time-to-market and higher quality silicon.
• position Synopsys as a trusted partner and thought leader in physical design, strengthening long-term customer relationships and industry reputation.
• Facilitate knowledge transfer and skill development within the team, raising the overall competency and effectiveness of the Applications Engineering group.
• Contribute to Synopsys’ business growth by showcasing the value and differentiation of Synopsys tools in competitive engagements and benchmark evaluations.

What You’ll Need:

• Bachelor’s and/or Master’s degree in Electrical Engineering or a related field.
• 15+ plus years of experience with the complete RTL-to-GDS physical design flow, including advanced nodes.
• Proficiency with industry-standard EDA tools: Fusion Compiler, PrimeTime, PrimeClosure, Formality, DSO.ai, FusionAI, ICV, StarRC, RTLA, and familiarity with Innovus, Genus, Tempus, Quantus, Cerebrus.
• In-depth understanding of synthesis, design planning, place & route, timing closure, power reduction, DRC rules, static timing analysis, and ECO methodologies.
• Experience with LLMs, GPT models, and other generative AI techniques.
• Strong analytical and problem-solving skills, with the ability to diagnose and resolve complex design and tool issues.

Who You Are:

• Innovative, resourceful, and proactive in driving technical solutions and continuous improvement.
• Excellent communicator, able to clearly articulate technical concepts to diverse audiences.
• Collaborative team player who thrives in a fast-paced, cross-functional environment.
• Customer-focused mindset with a passion for delivering exceptional support and building lasting relationships.
• Effective mentor and knowledge sharer, committed to uplifting the team and advancing organizational goals.